The instant invention pertains to semiconductor device fabrication and processing and more specifically to a method of integrating implantation steps so as to form high-performance, high-reliability devices.
Implantation of dopants into the semiconductor substrate (or epitaxial silicon layer which overlies the semiconductor substrate) is important in semiconductor device fabrication. Many different implantation steps need to be performed so as to: dope the polycrystalline silicon (xe2x80x9cpolyxe2x80x9d or xe2x80x9cpolysiliconxe2x80x9d) gate structure, form drain extensions, form pockets, form source and drain regions, form isolation structures, and to increase or decrease the conductivity of semiconductor structures. A problem with all of these implantation steps is that they may require separate masks so as to block the implantation of dopants from one region while exposing other regions to the implantation of dopants. Formation of these masks is very expensive and can be quite difficult to implement due to the ever-shrinking feature sizes and the difficulties associated with present limitations on photolithography. Some relief from these problems can be achieved by using existing structures to act as masks for the implantation of dopants. For example, the gate structure (not including a sidewall spacer) and the isolation structures can be used to define the region where the drain extensions are formed. In addition, the isolation structures and the gate structure, which includes a sidewall spacer, can be used to define the region in which dopants are implanted to form the source and drain regions. However, this self-alignment methodology can not solve all of the problems related to precisely implanting dopants into these semiconductor structures.
In semiconductor chips which utilizes many different types of devices, such as nMOS and pMOS logic transistors, higher bias voltage transistors, analog transistors, and others, many different masks are used to form the various doped regions. For example, the drain extensions (also referred to as xe2x80x9clightly doped drain extensionsxe2x80x9d or xe2x80x9cLDD""sxe2x80x9d) are typically formed separately for each device type. In additions, the pocket implants are formed separately, as are the source/drain implants. With all of these different masks, the process becomes quite complex (especially since all of these mask are critical masks) and quite expensive.
Hence, there is a need for a methodology which will result in the implantation to form a structure in one device without damaging other exposed structures (which would not have typically been doped with this dopant) while reducing the number of masking steps required to make a plurality of different device types.
The invention is a method for fabricating an integrated circuit having analog and digital core devices. Using a first masking layer, a first conductivity type dopant is implanted into the first (e.g., pMOS) digital core transistor region and the first (e.g., pMOS) analog core region. I/O transistors may also be implanted. Using a second masking layer, a second conductivity type dopant is implanted into at least a drain side of a second (e.g., nMOS) analog core region and the first (e.g., pMOS) digital core region. This forms a pocket region in the digital core region but not the analog core region or the I/O region.
An advantage of the invention is providing a method for fabricating an integrated circuit having pMOS and nMOS core digital devices, nMOS and pMOS core analog devices and, if desired, nMOS and pMOS I/O devices using only one additional mask from that required to for the pMOS and nMOS core digital devices.